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SRAM / Semiconductor Layout Engineer

IBM

IBM

Posted on Wednesday, October 18, 2023
Introduction
As a Hardware Developer at IBM, you’ll get to work on the systems that are driving the quantum revolution and the AI era. Join an elite team of engineering professionals who enable IBM customers to make better decisions quicker on the most trusted hardware platform in today’s market.

Your Role and Responsibilities

IBM Research at Albany, NY is looking for a Hardware Development Engineer to support the development of memory bit cell technology elements integrated into next-generation advanced CMOS technology nodes.
The responsibilities for this position include:
• Generation, maintenance and version control of physical layout for memory bitcell kits and test chip content
• Refining the memory cell array design in accordance with new technology process assumptions, reliability requirements, and future product-design needs.
• Close collaboration with process integration, patterning and module teams to ensure that the cell and array performance is aligned with evolving CMOS process development.
• Definition of electrical test structures for SRAM memory cell and array characterization
• Close collaboration with integration and patterning engineering teams to assure robust manufacturability of physical layouts
• Device simulations to determine memory cell optimization for incorporation into product designs.
• Accounting for memory array Design Rule Checking (DRC) wavers for inclusion in technology documentation

Required Technical and Professional Expertise

• Strong background in physical layout of semiconductor memory elements or similar.
• 2+ years experience with layout using industry-standard layout tools such as Cadence or Synopsys
• 2+ years of experience with Design Rule Checking (DRC) and with LVS (Layout versus schematic) industry standard tools and methods
• 2+ years of experience with CMOS design and CMOS process flows.
• 1+ years experience with SRAM bitcell physical layout

Preferred Technical and Professional Expertise

• 3+ years experience with SRAM array design
• 1+ years of experience with simulation software tools such as TCAD, Spice.
• 1+ years of experience with electrical test and test concepts, probe stations and parametric analyzers such as Keithley.
• 1+ years experience with layout design automation tools and methods
• 1+ years experience with machine learning tools and methods applied to physical layout
• Basic experience in analyzing large amounts of data using standard tools and programming languages such as JMP, SAS, Python, or similar tools.